The exemplary embodiments of this invention relate generally to memory in semiconductor devices and, more particularly, to a strap connection structure for connecting an embedded dynamic random access memory (eDRAM) to a transistor.
A complementary metal oxide semiconductor device (CMOS) uses symmetrically-oriented pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) arranged on silicon or silicon-on-insulator (SOI) substrates. Source and drain regions associated with the MOSFET are connected by a channel. A gate disposed over the channel controls the flow of current between the source and drain regions. The channel may be defined by a thin “fin” that provides more than one surface through which the gate controls the flow of current, thereby making the MOSFET a “finFET” device.
Dynamic random access memory (DRAM) employs memory cells having a finFET (or other type of transistor) and a storage capacitor arranged in series. Embedded DRAM (eDRAM) embeds these memory cells into the same semiconducting material that contains a microprocessor, which allows for wider buses and faster operating speeds (as compared to DRAM) in an integrated circuit (IC) chip. Many of these embedded memory cells comprising finFETs and storage capacitors can be arranged on a single chip or within a single package to define an array. Operation of the memory cells is controlled by various circuits, many of which are structurally different from each other, and warrant different manufacturing techniques.